Senior Principal Mixed-Signal Verification Lead

Renesas Electronics; Plano (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Renesas Electronics is seeking a Principal Verification Engineer to lead verification for our Automotive PMIC product line in Plano, TX. The role combines deep mixed-signal expertise with leadership to mentor engineers and drive verification strategy across platforms.

The ideal candidate has 12+ years in mixed-signal/analog verification, hands-on RNM and AMS integration, and strong RTL/GLS skills with Verilog/SystemVerilog. Automotive PMIC experience is a plus.

Qualifications

• 12+ years of experience in mixed-signal or analog circuit verification.
• Deep understanding of mixed-signal verification environment architecture and implementation.
• Hands-on experience with RNM and AMS model integration.
• Proficiency in Verilog, SystemVerilog, and SPICE-based languages.

Responsibilities

• Design and architect mixed-signal verification environments for PMIC designs.
• Develop verification plans and strategies meeting automotive safety standards (ISO 26262, AEC-Q200).
• Set up and optimize GLS flows, correlate RTL with GLS results to resolve discrepancies.
• Lead debugging for analog blocks (switched‑mode regulators, LDO, bandgap).
• Analyze timing, power, and functional correctness across PVT corners.
• Collaborate with Design, ATE, Silicon Validation for smooth handoffs.
• Mentor junior verification engineers and establish best practices.

Skills

Mixed-signal verification

RTL/behavioral simulation

UVM verification

Debugging analog & digital blocks

Leadership & mentoring

Automotive PMIC design

Verilog/SystemVerilog

Gate-Level Simulation (GLS)

RNM/AMS modeling

Measurement & test techniques

Education

MS or PhD in Electrical Engineering

Tools

Spectre

Xcelium

Job description

Renesas Electronics is seeking a Principal Verification Engineer to lead verification for our Automotive PMIC product line in Plano, TX. The role combines deep mixed-signal expertise with leadership to mentor engineers and drive verification strategy across platforms.

The ideal candidate has 12+ years in mixed-signal/analog verification, hands-on RNM and AMS integration, and strong RTL/GLS skills with Verilog/SystemVerilog. Automotive PMIC experience is a plus.