Senior SoC Verification Engineer - UVM

Renesas Electronics; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Renesas Electronics seeks a Senior Digital Design Verification Engineer to own verification of complex power-management SoCs, combining digital control, telemetry, fault management, and configurable peripherals for AI and enterprise systems.

You will develop and maintain SystemVerilog/UVM environments, create constrained-random tests, drive coverage closure, and work with architecture, RTL, firmware, and validation teams to deliver robust, bug-free silicon.

Qualifications

• 4+ years of relevant digital design verification experience.
• Ownership of a complex block, subsystem, or major feature from verification planning through closure.
• Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.
• Experience translating specifications into test plans, test scenarios, checkers, scoreboards, assertions, coverage models, and closure criteria.
• Hands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures.
• Strong RTL and testbench debug skills, with the ability to distinguish design, environment, test, firmware, and specification issues.
• Working knowledge of digital design fundamentals, including state machines, clocks, resets, interrupts, register interfaces, memories, and clock-domain crossings.
• Proficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl.
• Ability to work independently and collaborate effectively across architecture, design, firmware, analog, validation, and systems teams.

Responsibilities

• Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
• Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.
• Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.
• Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.
• Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.
• Debug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes.
• Automate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools.
• Communicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers.

Skills

SystemVerilog

UVM

Constrained random verification

Functional coverage

SystemVerilog Assertions

RTL and testbench debug

Python

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Xcelium

SimVision

vManager

JasperGold

Synopsys VCS

Verdi

Job description

Renesas Electronics seeks a Senior Digital Design Verification Engineer to own verification of complex power-management SoCs, combining digital control, telemetry, fault management, and configurable peripherals for AI and enterprise systems.

You will develop and maintain SystemVerilog/UVM environments, create constrained-random tests, drive coverage closure, and work with architecture, RTL, firmware, and validation teams to deliver robust, bug-free silicon.