Senior Memory Subsystem Verification Engineer

Nutanix; Santa Clara (CA); On-site; USD 153,000 - 230,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a motivated Design Verification Engineer to join its memory subsystem verification team.

You will develop verification strategies, build UVM-based testbenches, and drive coverage closure for high-performance memory interfaces (LPDDR/DDR/HBM) and related PHY logic. The role emphasizes hands-on verification with Verilog, SystemVerilog, UVM, and SVA, spanning the full verification lifecycle from planning to regression and debug.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 4+ years of ASIC design verification or related work.
• Experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
• Knowledge of LPDDR, DDR, HBM, JEDEC specs and memory interfaces.
• Strong analytical and collaboration skills.

Responsibilities

• Develop verification strategies, test plans, and coverage plans for complex RTL designs.
• Build, enhance, and maintain reusable SystemVerilog/UVM environments.
• Develop and maintain UVM components: sequences, drivers, monitors, scoreboards, agents, and coverage models.
• Create constrained-random, directed, and corner-case tests; inject errors as needed.
• Write and maintain SystemVerilog Assertions for protocol and timing checks.
• Analyze simulation failures and perform root-cause analysis with cross-functional teams.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Memory verification

Constrained-random testing

Education

Bachelor's degree

Master's degree

PhD

Tools

UPF

Job description

Qualcomm Technologies, Inc. is seeking a motivated Design Verification Engineer to join its memory subsystem verification team.

You will develop verification strategies, build UVM-based testbenches, and drive coverage closure for high-performance memory interfaces (LPDDR/DDR/HBM) and related PHY logic. The role emphasizes hands-on verification with Verilog, SystemVerilog, UVM, and SVA, spanning the full verification lifecycle from planning to regression and debug.