Senior Design Verification Engineer – Memory Controller Subsystem (HBM)

ALTEN; San Jose (CA); On-site; USD 120,000 - 155,000; Full time

Job summary

ALTEN is seeking an experienced Verification Engineer in California to verify HBM memory controller subsystems using SystemVerilog/UVM. The role involves developing verification plans, UVM testbenches, and test cases, while validating ECC, QoS, power management, and performance metrics.

The engineer will collaborate with Architecture and Validation teams to drive regression and coverage closure, ensuring signoff on complex hardware subsystems.

Qualifications

• Proven expertise in SystemVerilog/UVM verification.
• Experience verifying DDR/HBM memory controllers or subsystems.
• Strong knowledge of HBM/DDR protocols, AXI interfaces, and memory architecture.
• Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
• Proficient with simulators Xcelium, VCS, Questa and scripting (Python/Perl/Shell).

Responsibilities

• Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Skills

SystemVerilog/UVM expertise

DDR/HBM memory verification

HBM/DDR protocols & AXI

Assertions & constrained-random

Scripting (Python/Perl/Shell)

Tools

Xcelium

VCS

Questa

Python

Perl

Shell

Job description

Experience: 5–12+ Years

Responsibilities

• Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Required Skills

• Strong SystemVerilog/UVM expertise.
• Experience verifying DDR/HBM memory controllers or memory subsystems.
• Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
• Experience with assertions, constrained‑random verification, coverage closure, and VIP integration.
• Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).