Senior Memory Layout Engineer for Next-Gen CMOS SRAM

ITCO Solutions, Inc.; California; Presencial; USD 140 000 - 190 000; Tempo integral

Resumo da oferta

ITCO Solutions, Inc. is seeking a Senior Custom Memory Layout Engineer to design and integrate memory periphery, sense circuitry, and macro interfaces in advanced CMOS tech. You will lead layout efforts, collaborate with circuit and CAD teams, and mentor junior engineers.

The role requires hands-on memory-layout expertise, knowledge of LOD and density/fill effects, and experience with tapeout readiness. Onsite with potential hybrid after ramp-up, in California.

Qualificações

• 5+ years of hands-on custom IC layout experience.
• 1–3+ years with SRAM or memory IP.
• Direct experience creating custom layouts, not just managing layout teams.
• Experience with TSMC 3nm or more advanced process technology.
• Strong Calibre, ICV, or equivalent physical verification.
• Experience with floorplanning, routing, macro assembly, pin planning, and top-level integration.
• BSEE or equivalent.

Responsabilidades

• Create custom layouts for memory periphery, test structures, and memory macros.
• Develop block floorplans, routing strategies, power grids, and macro interfaces.
• Translate schematics into high-quality physical layouts while maintaining matching, symmetry, shielding, and parasitic requirements.
• Perform and debug DRC, LVS, ERC, antenna, and physical verification.
• Support EM/IR, DFM, density/fill, dummy insertion, and tapeout requirements.
• Resolve integration, pin-access, boundary, routing, and top-level physical-design issues.
• Work with circuit design, CAD, PnR, integration, and foundry teams.
• Review designs and mentor less-experienced layout engineers.

Conhecimentos

IC layout

Custom memory layout

Floorplanning

Routing

Physical verification

Formação académica

BSEE or equivalent

Ferramentas

Calibre

ICV

Descrição da oferta de emprego

ITCO Solutions, Inc. is seeking a Senior Custom Memory Layout Engineer to design and integrate memory periphery, sense circuitry, and macro interfaces in advanced CMOS tech. You will lead layout efforts, collaborate with circuit and CAD teams, and mentor junior engineers.

The role requires hands-on memory-layout expertise, knowledge of LOD and density/fill effects, and experience with tapeout readiness. Onsite with potential hybrid after ramp-up, in California.