Senior Layout Engineer

ITCO Solutions, Inc.; California; Sur place; USD 140 000 - 190 000; Plein temps

Résumé du poste

ITCO Solutions, Inc. is seeking a Senior Custom Memory Layout Engineer to design and integrate memory periphery, sense circuitry, and macro interfaces in advanced CMOS tech. You will lead layout efforts, collaborate with circuit and CAD teams, and mentor junior engineers.

The role requires hands-on memory-layout expertise, knowledge of LOD and density/fill effects, and experience with tapeout readiness. Onsite with potential hybrid after ramp-up, in California.

Qualifications

• 5+ years of hands-on custom IC layout experience.
• 1–3+ years with SRAM or memory IP.
• Direct experience creating custom layouts, not just managing layout teams.
• Experience with TSMC 3nm or more advanced process technology.
• Strong Calibre, ICV, or equivalent physical verification.
• Experience with floorplanning, routing, macro assembly, pin planning, and top-level integration.
• BSEE or equivalent.

Responsabilités

• Create custom layouts for memory periphery, test structures, and memory macros.
• Develop block floorplans, routing strategies, power grids, and macro interfaces.
• Translate schematics into high-quality physical layouts while maintaining matching, symmetry, shielding, and parasitic requirements.
• Perform and debug DRC, LVS, ERC, antenna, and physical verification.
• Support EM/IR, DFM, density/fill, dummy insertion, and tapeout requirements.
• Resolve integration, pin-access, boundary, routing, and top-level physical-design issues.
• Work with circuit design, CAD, PnR, integration, and foundry teams.
• Review designs and mentor less-experienced layout engineers.

Connaissances

IC layout

Custom memory layout

Floorplanning

Routing

Physical verification

Formation

BSEE or equivalent

Outils

Calibre

ICV

Description du poste

Memory Layout Engineers needed, Sr, Midlevel and Jr engineers – All Welcome!

Contract: 12 Months - Contract to hire

Work Setting: Onsite initially; hybrid may be possible after ramp-up

TSMC alumni is a major plus!

Role Overview

Seeking a Senior Custom Memory Layout Engineer to develop and integrate memory periphery, sense circuitry, control structures, test structures, and memory macros in advanced CMOS technologies. The role requires deep hands-on custom layout experience and close collaboration with circuit and physical-design teams.

Responsibilities

• Create custom layouts for memory periphery, test structures, and memory macros.
• Develop block floorplans, routing strategies, power grids, and macro interfaces.
• Translate schematics into high-quality physical layouts while maintaining matching, symmetry, shielding, and parasitic requirements.
• Perform and debug DRC, LVS, ERC, antenna, and physical verification.
• Support EM/IR, DFM, density/fill, dummy insertion, and tapeout requirements.
• Resolve integration, pin-access, boundary, routing, and top-level physical-design issues.
• Work with circuit design, CAD, PnR, integration, and foundry teams.
• Review designs and mentor less-experienced layout engineers.

Required Qualifications

• 5+ years of hands-on custom IC layout experience.
• 1-3+ years working with SRAM, memory IP, or custom digital memory layout.
• Direct experience creating custom layouts rather than primarily managing layout teams.
• Experience with TSMC 3nm or more advanced process technology.
• Strong Calibre, ICV, or equivalent physical-verification experience.
• Experience with floorplanning, routing, macro assembly, pin planning, and block/top-level integration.
• Knowledge of advanced-node effects including LOD, density/fill, EM/IR, DFM, matching, and parasitic control.
• BSEE or equivalent experience.

Preferred

• Experience with TSMC, Samsung, Micron, or other advanced semiconductor organizations.
• Beyond-3nm experience.
• Experience with memory compilers or reusable memory IP.
• Exposure to AI-assisted custom-layout methodologies.