Senior Memory Design Engineer - SRAM & Compiler Lead

UANDWE, Inc.; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

UANDWE, Inc. is seeking an experienced memory design engineer to contribute to and lead the development of SRAM and register-file compilers for 2–5nm technology. You will circuit-design key components, simulate critical paths, and drive margins and sign-off to meet yield and performance targets.

The role emphasizes silicon debugging, advanced layout considerations, and utilization of Cadence/Mentor tools. You will perform detailed timing and reliability analyses and contribute to memory DFT

Qualifications

• Expert in high-speed CMOS circuit design and clocking schemes.
• Experience delivering memory compiler specifications to final release.
• Deep knowledge of split rail and power gating architectures.
• Hands-on silicon debugging and fault analysis.
• Proficient with Cadence/Mentor schematic and layout tools.
• Circuit simulation and waveform analysis with HSPICE/HSIM/XA/FinSim/XARA/nWave.
• Scripting experience in Perl/Python is a plus.
• Understanding sub-nanometer layout design challenges is a must.
• Knowledge of Memory DFT is a plus.
• Masters degree with 2+ years or Bachelor with 3+ years.

Responsibilities

• Lead design and development of SRAM and register-file compilers in advanced nodes.
• Circuit design/simulation of key memory components such as bitcell, WL decoder, SAMP, column decoder and control logic.
• Develop margin and characterization flows for detailed simulations.
• Statistical analysis of Bit-Cell and Sense Amplifier for compiler yield sign-off.
• Design tuning, margin analysis and sign-off to meet yield and performance targets.
• Logic simulations and timing analysis of critical paths in high-speed memory designs.
• Signal-Integrity and Power-Integrity analysis and design.

Skills

High-speed CMOS design

Memory compiler design

Power gating architecture

Silicon debugging

Cadence/Mentor tools

Circuit simulation

Scripting: Perl/Python

Sub-nanometer layout challenges

Memory DFT

Advanced degree requirement

Education

Master's Degree in Electrical Engineering

Bachelor's Degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

HSPICE

HSIM

XA

FinSim

XARA

nWave

Job description

UANDWE, Inc. is seeking an experienced memory design engineer to contribute to and lead the development of SRAM and register-file compilers for 2–5nm technology. You will circuit-design key components, simulate critical paths, and drive margins and sign-off to meet yield and performance targets.

The role emphasizes silicon debugging, advanced layout considerations, and utilization of Cadence/Mentor tools. You will perform detailed timing and reliability analyses and contribute to memory DFT