Senior Memory Design Engineer

UANDWE, Inc.; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

UANDWE, Inc. is seeking an experienced memory design engineer to contribute to and lead the development of SRAM and register-file compilers for 2–5nm technology. You will circuit-design key components, simulate critical paths, and drive margins and sign-off to meet yield and performance targets.

The role emphasizes silicon debugging, advanced layout considerations, and utilization of Cadence/Mentor tools. You will perform detailed timing and reliability analyses and contribute to memory DFT

Qualifications

• Expert in high-speed CMOS circuit design and clocking schemes.
• Experience delivering memory compiler specifications to final release.
• Deep knowledge of split rail and power gating architectures.
• Hands-on silicon debugging and fault analysis.
• Proficient with Cadence/Mentor schematic and layout tools.
• Circuit simulation and waveform analysis with HSPICE/HSIM/XA/FinSim/XARA/nWave.
• Scripting experience in Perl/Python is a plus.
• Understanding sub-nanometer layout design challenges is a must.
• Knowledge of Memory DFT is a plus.
• Masters degree with 2+ years or Bachelor with 3+ years.

Responsibilities

• Lead design and development of SRAM and register-file compilers in advanced nodes.
• Circuit design/simulation of key memory components such as bitcell, WL decoder, SAMP, column decoder and control logic.
• Develop margin and characterization flows for detailed simulations.
• Statistical analysis of Bit-Cell and Sense Amplifier for compiler yield sign-off.
• Design tuning, margin analysis and sign-off to meet yield and performance targets.
• Logic simulations and timing analysis of critical paths in high-speed memory designs.
• Signal-Integrity and Power-Integrity analysis and design.

Skills

High-speed CMOS design

Memory compiler design

Power gating architecture

Silicon debugging

Cadence/Mentor tools

Circuit simulation

Scripting: Perl/Python

Sub-nanometer layout challenges

Memory DFT

Advanced degree requirement

Education

Master's Degree in Electrical Engineering

Bachelor's Degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

HSPICE

HSIM

XA

FinSim

XARA

nWave

Job description

Job Details: Location; San Jose CA/San Diego CA/Culver City CA/Irvine CA (onsite)

• 1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 2/3/4/5nm Technologies
• 2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
• 3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.
• 4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
• 5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
• 6) Logic simulations and detailed timing analysis of key paths in high speed memory design.
• 7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.

Skill Sets/Prerequisites

• 1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
• 2) Experience in Designing and driving one or many Memory Compilers Specifications to final release
• 3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
• 4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.
• 5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools
• 6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
• 7) Experience in Skill/Perl/Python Scripting is a strong plus
• 8) Experience in Understanding the layout design issues in sub nanometer regime is a must.
• 9. Expertise in Understanding Memory DFT is a Plus.
• 10. Masters Degree with 2+ Years or Bachelors Degree with 3+ years