Senior SRAM Circuit Design Engineer — High-Performance Memory

Samsung Semiconductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

4+ weeks paid time off

Medical/Dental/Vision/401k

Charitable giving match

Fertility/adoption stipend

Onsite café & gym

Job summary

Samsung Semiconductor in San Jose, CA seeks a Staff Engineer, SRAM Circuit Design to lead end-to-end SRAM memory design for future devices. You will develop bit cells, decoders, sense amplifiers and write/read paths for 2nm-5nm nodes while optimizing performance, power and area and mentoring junior engineers.

Collaborate with product, test, layout and technology teams, run extensive circuit simulations using HSPICE/Spectre and Cadence tools, and contribute to patents and technical publications.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of industry experience or master's with 8+ years strongly preferred.
• Experience in SRAM or memory circuit design with advanced process nodes.
• Strong understanding of device physics and process technology (FinFET, GAA, SOI).

Responsibilities

• Design and develop SRAM memory arrays, bit cells, sense amps, decoders and control circuits for 2nm–5nm nodes.
• Optimize SRAM designs for performance, power and area (PPA) and yield.
• Develop layouts and perform physical design verifications (DRC, LVS) and support silicon bring-up.

Skills

SRAM design

Memory circuit design

Circuit simulation

Leadership

Team collaboration

Scripting (Python)

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Spectre

HSPICE

Cadence Virtuoso

Cadence design tools

Job description

Samsung Semiconductor in San Jose, CA seeks a Staff Engineer, SRAM Circuit Design to lead end-to-end SRAM memory design for future devices. You will develop bit cells, decoders, sense amplifiers and write/read paths for 2nm-5nm nodes while optimizing performance, power and area and mentoring junior engineers.

Collaborate with product, test, layout and technology teams, run extensive circuit simulations using HSPICE/Spectre and Cadence tools, and contribute to patents and technical publications.