Lead Custom Memory Design Engineer: SRAMs & Register Files

NUVACORE; Santa Clara, Northern (CA, KY); Hybrid; USD 180,000 - 230,000; Full time

Job summary

NUVACORE in Santa Clara is seeking a Custom Memory Design Engineer to drive SRAM and Register Files design across the full memory IP flow, from schematic to signoff, collaborating with RTL, CAD, and foundry teams.

You will own layout supervision, PDV closure, and end-to-end signoff (DRC/LVS/antenna, extraction, timing and power) at advanced CMOS nodes, with a track record delivering production‑level memory IP.

Qualifications

• BS or MS degree in a relevant field with 8+ years in custom memory circuit design (SRAM/Register File).
• Hands-on transistor-level circuit design with memory arrays, sense amps, decoders in advanced CMOS nodes.
• Deep knowledge of SPICE simulations and memory margins for SRAM/Register File.
• Proficient with industry-standard EDA tools for schematic, layout, extraction, characterization.
• Track record delivering production-level custom memory IP through tape-out with silicon-validated PPA.
• Deep end-to-end signoff experience (DRC/LVS/antenna, extraction, STA, EM/IR).
• Strong collaboration skills with foundry, CAD, and physical design teams.

Responsibilities

• Own schematic development and characterize custom memories (SRAM, register files) to optimize PPA.
• Supervise layout implementation, macro floor planning, routing specs, and PDV closure.
• Own end-to-end memory IP signoff across DRC/LVS/antenna, extraction, timing, power, and noise.
• Partner with Foundry/PDK, CAD, Physical Design, RTL and DFT teams to benchmark tech and co-optimize memories.
• Collaborate with RTL to define memory functional specs and timing behaviors for RTL modeling.
• Define and drive tools, flows, and methodology (TFM) to raise design efficiency and best practices.

Skills

Memory design

Schematic design

Transistor-level design

SPICE simulations

EDA tools

IP tape-out

Signoff - DRC/LVS/Antenna

RTL collaboration

Communication & cross-team

Education

BS or MS in ECE/related field

Tools

EDA tools

Job description

NUVACORE in Santa Clara is seeking a Custom Memory Design Engineer to drive SRAM and Register Files design across the full memory IP flow, from schematic to signoff, collaborating with RTL, CAD, and foundry teams.

You will own layout supervision, PDV closure, and end-to-end signoff (DRC/LVS/antenna, extraction, timing and power) at advanced CMOS nodes, with a track record delivering production‑level memory IP.