Senior Cache Coherence Architect - Equity & Impact

NVIDIA Corporation; Santa Clara (CA); On-site; USD 152,000 - 288,000; Full time

Benefits offered by this job

Equity and benefits

Job summary

NVIDIA seeks an experienced Senior Cache Coherency Architect to join our team in shaping scalable, low-latency coherent interconnects powering Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin. You will define coherence protocols and interconnect interfaces aligned with powerful CPU/GPU architectures.

You will model and implement cache-coherent subsystems, collaborate with IP creation and verification teams, and support post-silicon debug to ensure room‑wide PPA adherence across

Qualifications

• Master’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in processor design or other high-performance semiconductor designs.
• Deep understanding of cache coherency, with hands-on experience in industry-standard protocols (e.g., AXI, ACE, CHI).
• Experience authoring specifications and designing cache-coherent interconnects.
• Strong understanding of system and memory subsystem architecture, with a focus on cache-coherent interconnect.
• Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
• Proficiency in C, C++, Python, and Verilog.

Responsibilities

• Define consistent interconnect architecture, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
• Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache-coherency compliance.
• Collaborate with architects to guarantee the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
• Develop and maintain functional and performance models for the NoC fabric and IP units to assist with analysis and validation.
• Collaborate with cross-functional design and verification teams (simulation, emulation, and formal) to ensure implementations align with architectural specifications.
• Support silicon bring-up and post-silicon debug as needed.

Skills

Cache coherency

AXI/ACE/CHI protocols

System/memory architecture

Coherent IP models

C/C++/Python/Verilog

Education

Master’s degree in Electrical/Computer Engineering or Computer Science

Tools

VIPs

BFMs

Simulation

Job description

NVIDIA seeks an experienced Senior Cache Coherency Architect to join our team in shaping scalable, low-latency coherent interconnects powering Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin. You will define coherence protocols and interconnect interfaces aligned with powerful CPU/GPU architectures.

You will model and implement cache-coherent subsystems, collaborate with IP creation and verification teams, and support post-silicon debug to ensure room‑wide PPA adherence across