Lead NoC IP Architect for Scalable FPGA Platforms

191 Altera Corporation; San Jose (CA); On-site; USD 209,500 - 299,200; Full time

Job summary

Altera Corporation in the San Jose area seeks a Principal NoC IP Micro-Architect to lead end-to-end architecture, microarchitecture, RTL design and technical leadership of NoC IPs for next-generation FPGA platforms.

You will collaborate with architecture, design, verification, software, physical design and product teams to deliver high-performance interconnect solutions optimized for power, performance, area, and reliability.

Qualifications

• Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of related experience, including 10+ years in SystemVerilog, VCS/Synopsys simulators, lint, and synthesis.
• 10+ years programming experience with C/C++, Perl, Python, TCL, and Unix Shell scripting.
• 10+ years in FPGA design and programming (plus RTL validation experience). 10+ years developing Network on Chip IPs.
• 5+ years using AI to improve development efficiency (plus).

Responsibilities

• Develop logic design, RTL coding, and simulation for Network on Chip IPs and other FPGA IPs/subsystems for integration into full chip designs.
• Participate in defining the architecture and microarchitecture features of the block being designed.
• Create prototypes, simulate models, specify system requirements, and deliver software models for device‑level bring‑up, including user‑visible functionality, timing, and power.
• Apply RTL implementation techniques to qualify designs to meet power, performance, and area goals, partnering with the physical implementation team.
• Use advanced EDA tools (timing constraints, verification, RTL lint, CDC, RDC, DFT) to ensure high‑quality IP development and automate processes to enhance efficiency.
• Review verification plans and implementations, resolve errors, and implement corrective measures for failing RTL tests to ensure feature correctness.
• Mentor junior team members, oversee the NoC team, and proactively identify and mitigate design challenges to meet project requirements and schedule.

Skills

SystemVerilog

VCS/Synopsys simulators

C/C++

Python

Perl

TCL

FPGA design

NoC/IPs

AI for development efficiency

Education

Bachelor's or Master’s Degree in Electrical Engineering or Computer Engineering

Tools

lint

synthesis

Job description

Altera Corporation in the San Jose area seeks a Principal NoC IP Micro-Architect to lead end-to-end architecture, microarchitecture, RTL design and technical leadership of NoC IPs for next-generation FPGA platforms.

You will collaborate with architecture, design, verification, software, physical design and product teams to deliver high-performance interconnect solutions optimized for power, performance, area, and reliability.