Senior Lead FPGA/SoC Architect — High-Impact Design

Altera; San Jose (CA); On-site; USD 232,000 - 330,000; Full time

Job summary

Altera is seeking a Senior Lead Design Engineer to provide hands‑on technical leadership for FPGA/SoC architectures and RTL delivery. You will define high‑throughput datapaths, interfaces, and reusable IP, guiding architecture through RTL, verification, and post‑silicon validation.

You will collaborate with cross‑functional teams across architecture, CAD, firmware, and software to ensure product objectives are met and performance targets achieved.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 15+ years of relevant FPGA/ASIC/SoC or semiconductor product development experience; advanced degree preferred.
• Strong hands‑on experience in Verilog/SystemVerilog RTL design, synthesis, lint, timing constraints, and post‑silicon validation.
• Proven leadership delivering complex digital subsystems or products from architecture to RTL, verification, and bring‑up.
• Experience with high‑performance digital architectures (PCIe/CXL, Ethernet, memory subsystems) and data center acceleration.

Responsibilities

• Lead architecture, microarchitecture, and RTL development for complex FPGA and programmable SoC subsystems.
• Define interfaces, specifications, and implementation plans aligning hardware, firmware, software, validation, and product goals.
• Drive tradeoffs across performance, power, area, latency, bandwidth, and reliability using data and analysis.
• Own blocks through RTL, synthesis, integration, and bring‑up, including timing closure and performance characterization.
• Establish reusable IP, coding standards, automation, and quality methodologies to improve velocity and predictability.
• Collaborate with architecture, design verification, physical design, CAD, firmware/software, and post‑silicon teams to maintain architectural intent.
• Lead cross‑functional issue resolution with root‑cause analysis and debugging strategies.
• Provide mentorship and design leadership across teams; drive architecture reviews and code reviews.
• Influence roadmaps and partner on IP, tools, and tech choices to strengthen Altera’s programmable portfolio.

Skills

FPGA

ASIC

SoC development

RTL design

Verilog/SystemVerilog

Architecture definition

Debug/diagnostics

Leadership

High‑performance digital

Networking/PCIe

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

None

Job description

Altera is seeking a Senior Lead Design Engineer to provide hands‑on technical leadership for FPGA/SoC architectures and RTL delivery. You will define high‑throughput datapaths, interfaces, and reusable IP, guiding architecture through RTL, verification, and post‑silicon validation.

You will collaborate with cross‑functional teams across architecture, CAD, firmware, and software to ensure product objectives are met and performance targets achieved.