Senior Interconnect Architect (TileLink, Chisel)

SiFive, Inc.; Austin (TX); On-site; USD 158,760 - 194,040; Full time

Benefits offered by this job

Healthcare plans

Retirement plans

Paid time off

Job summary

A leading semiconductor company in Austin, Texas is seeking a Staff Hardware Engineer to design innovative CPU and interconnect IPs for RISC-V architecture. Ideal candidates have strong backgrounds in hardware design and software engineering. Responsibilities include architecting and implementing TileLink interconnects and enhancing cache controllers. The role offers a competitive salary range of $158,760 to $194,040, along with comprehensive benefits.

Qualifications

• Ability to architect solutions to connect bus fabrics of disparate protocols.
• Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Attention to detail and a focus on high-quality design.

Responsibilities

• Architect, design and implement enhanced TileLink interconnect and cache controllers.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework.
• Ensure knowledge sharing through documentation and collaborative design.

Skills

Knowledge of cache and cache coherency architectures and concepts

Experience with NoC or other interconnect fabrics

Familiarity with industry-standard bus protocols (AXI, AHB, APB, CHI)

Strong software engineering skills/background

Education

BS/MS in EE, CE, CS or a related technical discipline

Tools

Verilog

System Verilog

VHDL

Job description

A leading semiconductor company in Austin, Texas is seeking a Staff Hardware Engineer to design innovative CPU and interconnect IPs for RISC-V architecture. Ideal candidates have strong backgrounds in hardware design and software engineering. Responsibilities include architecting and implementing TileLink interconnects and enhancing cache controllers. The role offers a competitive salary range of $158,760 to $194,040, along with comprehensive benefits.