A leading hardware technology company in Boston is seeking a staff level hardware engineer to design innovative CPU and interconnect IP. The role involves architecting and implementing advanced interconnect designs, enhancing multi-core performance, and collaborating with verification teams. The ideal candidate should possess a strong background in RTL design using Verilog/SystemVerilog, proficient programming skills, and knowledge of bus protocols. This position offers a competitive salary range and comprehensive benefits including healthcare and retirement plans.
Qualifications
Strong background in hardware design and software engineering.
Proficient in creating high-quality RTL designs.
Experience with DSLs for hardware expression is a plus.
Responsibilities
Architect and implement TileLink interconnect and cache controllers.
Enhance designs for performance and multi-system coherence.
Collaborate with verification teams on thorough test plans.
Skills
Knowledge of cache and cache coherency architectures
Experience with NoC interconnect fabrics
Familiarity with bus protocols (AXI, AHB, APB, CHI)
Strong software engineering skills
Proficiency in Verilog/SystemVerilog/VHDL
Attention to detail
Ability to work well in teams
Education
BS/MS in EE, CE, CS or related technical discipline
Tools
Git
GitHub
Jira
Confluence
Job description
A leading hardware technology company in Boston is seeking a staff level hardware engineer to design innovative CPU and interconnect IP. The role involves architecting and implementing advanced interconnect designs, enhancing multi-core performance, and collaborating with verification teams. The ideal candidate should possess a strong background in RTL design using Verilog/SystemVerilog, proficient programming skills, and knowledge of bus protocols. This position offers a competitive salary range and comprehensive benefits including healthcare and retirement plans.