Principal Interconnect Architect - Chisel/TileLink IP

SiFive; Austin (TX); On-site; USD 231,444 - 282,876; Full time

Job summary

SiFive is seeking a principal-level hardware engineer to design industry-leading CPU and interconnect IP, driving the adoption of RISC‑V as the architecture of choice for SOC designs across a broad range of vertical applications. The role emphasizes massively configurable IP and generating hardware as configurable software generators using Chisel.

The candidate will architect and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and other infrastructure logic in RTL

Qualifications

• Experience with cache coherency architectures and NoC/interconnect fabrics.
• Familiarity with AXI/CHI/CXL/UCIe bus protocols.
• Strong RTL design skills in Verilog/SystemVerilog/VHDL.
• BS/MS in EE/CE/CS or related field.

Responsibilities

• Architect, design, and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel.
• Implement RTL generators so elements self‑configure to optimally connect to each other.
• Enhance future designs to provide higher performance, more efficient multicore and multisystem coherence.
• Design extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration, generation of documentation, verification testbenches, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
• Ensure knowledge sharing through creation and maintenance of great documentation and participation in a culture of collaborative design.

Skills

Cache architectures

Cache coherency

NoC interconnect

Interconnect fabrics

Bus protocols

RTL design (Verilog/SV/VHDL)

Scala/Chisel experience

DSLs / compiler infra

Unit tests / TDD

Software engineering (OO/FP)

Team collaboration

Education

BS/MS in EE, CE, CS or related

Tools

Git/GitHub

Jira

Confluence

Job description

SiFive is seeking a principal-level hardware engineer to design industry-leading CPU and interconnect IP, driving the adoption of RISC‑V as the architecture of choice for SOC designs across a broad range of vertical applications. The role emphasizes massively configurable IP and generating hardware as configurable software generators using Chisel.

The candidate will architect and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and other infrastructure logic in RTL