A leading technology company in Austin, Texas is seeking a staff level hardware engineer to design cutting-edge CPU and interconnect IP. Responsibilities include architecting tile interconnects and cache controllers, implementing RTL generators, and enhancing system coherence. Candidates should have strong skills in hardware design, familiarity with industry standards, and solid software engineering backgrounds. A BS/MS in a relevant field is required. Comprehensive benefits are provided along with a competitive salary range of $158,760 to $194,040.
Qualifications
Strong background in cache and cache coherency architectures.
Experience with NoC or interconnect fabrics.
Proficiency in object-oriented programming and templated metaprogramming.
Attention to detail with a focus on high-quality design.
Responsibilities
Architect and implement TileLink interconnect and cache controllers.
Integrate new designs into SiFive’s Chisel/FIRRTL framework.
Perform initial sandbox verification and collaborate on verification test plans.
Maintain excellent documentation through collaborative design.
Skills
Cache coherency architectures
NoC or interconnect fabrics
Industry-standard bus protocols (AXI, AHB, APB, CHI)
Object-oriented programming
Templated metaprogramming
Data modeling
Test-driven development
RTL design in Verilog/SystemVerilog/VHDL
Software engineering skills
Education
BS/MS in EE, CE, CS or related technical discipline
Tools
Git
GitHub
Jira
Confluence
Job description
A leading technology company in Austin, Texas is seeking a staff level hardware engineer to design cutting-edge CPU and interconnect IP. Responsibilities include architecting tile interconnects and cache controllers, implementing RTL generators, and enhancing system coherence. Candidates should have strong skills in hardware design, familiarity with industry standards, and solid software engineering backgrounds. A BS/MS in a relevant field is required. Comprehensive benefits are provided along with a competitive salary range of $158,760 to $194,040.