Lead TileLink & Interconnect Architect (Chisel)

SiFive, Inc.; Santa Clara (CA); On-site; USD 231,444 - 282,876; Full time

Benefits offered by this job

Healthcare benefits

Retirement plans

Paid time off

Job summary

SiFive, Inc. is seeking a principal-level hardware engineer to design industry-leading CPU and interconnect IP. This role involves working on customizable IP and enhances the RISC-V architecture for SOC designs across various applications.

The ideal candidate should have strong RTL design skills and a solid educational background. The position offers a competitive salary range and numerous benefits, including healthcare, paid time off, and more.

Qualifications

• Experience with NoC or other interconnect fabrics.
• Ability to architect solutions to connect bus fabrics of disparate protocols.
• Attention to detail and a focus on high-quality design.

Responsibilities

• Architect, design and implement an enhanced TileLink interconnect.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework.
• Ensure knowledge is shared via creation and maintenance of documentation.

Skills

Knowledge of cache and cache coherency architectures

Strong software engineering skills

Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL

Education

BS/MS in EE, CE, CS or a related technical discipline

Tools

Git/GitHub

Jira

Confluence

Job description

SiFive, Inc. is seeking a principal-level hardware engineer to design industry-leading CPU and interconnect IP. This role involves working on customizable IP and enhances the RISC-V architecture for SOC designs across various applications.

The ideal candidate should have strong RTL design skills and a solid educational background. The position offers a competitive salary range and numerous benefits, including healthcare, paid time off, and more.