A leading technology company in California is seeking a staff level hardware engineer passionate about designing cutting-edge CPU and interconnect IP to drive RISC-V adoption. You will architect and implement advanced interconnects, enhance performance, and integrate new designs into the Chisel framework. Ideal candidates will have strong RTL design skills and a solid software engineering background, preferably with experience in bus protocols and collaboration in a team-oriented environment. Competitive pay and benefits offered.
Qualifications
Strong software engineering background including object-oriented and functional programming.
Ability to architect solutions to connect bus fabrics of disparate protocols.
Experience with domain-specific languages for hardware design.
Responsibilities
Architect and design an enhanced TileLink interconnect.
Implement RTL generators for optimal self-configuration.
Integrate new design content into the Chisel/FIRRTL framework.
Skills
Cache and cache coherency architectures
NoC or interconnect fabrics
Bus protocols (AXI, AHB, APB, CHI)
Software engineering skills
RTL design in Verilog/SystemVerilog/VHDL
Attention to detail
Team collaboration
Education
BS/MS in EE, CE, CS or related technical discipline
Tools
Git
GitHub
Jira
Confluence
Job description
A leading technology company in California is seeking a staff level hardware engineer passionate about designing cutting-edge CPU and interconnect IP to drive RISC-V adoption. You will architect and implement advanced interconnects, enhance performance, and integrate new designs into the Chisel framework. Ideal candidates will have strong RTL design skills and a solid software engineering background, preferably with experience in bus protocols and collaboration in a team-oriented environment. Competitive pay and benefits offered.