Senior Interconnect Architect for TileLink NoC

SiFive; Santa Clara (CA); On-site; USD 231,444 - 282,876; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

SiFive is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOCs. You will build highly configurable RTL generators in Chisel/Scala, accelerating time‑to‑market and performance.

You will collaborate with verification teams, implement TileLink interconnects, manage cache coherence, and contribute to documentation and tooling within SiFive's Chisel/FIRRTL framework.

Qualifications

• Cache coherency architectures knowledge.
• NoC or interconnect fabrics experience.
• Proficiency with AXI/AHB/APB/CHI/CXL/UCIe protocols.
• HDL design in Verilog/SystemVerilog/VHDL.
• Strong OO/FP software skills and compiler knowledge.

Responsibilities

• Architect, design, and implement enhanced TileLink interconnect, cache controllers, bridges and uncore logic as RTL generators in Chisel.
• Implement RTL generators so elements self-configure to connect to each other.
• Enhance designs for higher performance and multicore coherence.
• Design extensive configurability as a first-class consideration.
• Integrate new design content into Chisel/FIRRTL framework; enable auto-configuration and documentation generation.
• Collaborate with verification team to create thorough verification test plans.
• Maintain documentation and contribute to a culture of collaborative design.

Skills

Cache coherency

NoC interconnect

Bus protocols (AXI/AHB/APB/CHI/CXL/UCI

RTL design (Verilog/SV/VHDL)

Software engineering: FP/OO

Data modeling

Education

BS/MS in EE/CE/CS

Tools

Git/GitHub

Jira

Confluence

Job description

SiFive is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOCs. You will build highly configurable RTL generators in Chisel/Scala, accelerating time‑to‑market and performance.

You will collaborate with verification teams, implement TileLink interconnects, manage cache coherence, and contribute to documentation and tooling within SiFive's Chisel/FIRRTL framework.