Senior Interconnect Architect for TileLink & Chisel RTL

SiFive; Boston (MA); On-site; USD 231,444 - 282,876; Full time

Benefits offered by this job

Healthcare and retirement plans

Paid time off

Variable compensation and equity

Job summary

SiFive is looking for a principal-level hardware engineer to enhance CPU and interconnect development. Applicants should have a background in RISC-V architecture and experience in RTL design. The role also involves working on scalable and customizable architectural solutions.

With a strong emphasis on collaboration, engineers will architect innovative designs that integrate efficiently within the existing framework. Competitive benefits and compensation are included.

Qualifications

• Knowledge of cache and cache coherency architectures is crucial.
• Experience with NoC or other interconnect fabrics preferred.
• Strong software engineering background is necessary.

Responsibilities

• Architect, design and implement TileLink interconnect and caches.
• Create self-configuring RTL generators in Chisel.
• Integrate designs into SiFive’s framework for documentation.

Skills

Cache architectures

Software engineering

Hardware design (Verilog/System Verilog/VHDL)

Objective-oriented programming

Education

BS/MS in EE, CE, CS or related discipline

Tools

Git/Github

Jira

Confluence

Job description

SiFive is looking for a principal-level hardware engineer to enhance CPU and interconnect development. Applicants should have a background in RISC-V architecture and experience in RTL design. The role also involves working on scalable and customizable architectural solutions.

With a strong emphasis on collaboration, engineers will architect innovative designs that integrate efficiently within the existing framework. Competitive benefits and compensation are included.