Senior IC Verification Engineer - SystemVerilog/UVM Expert

Broadcom, Inc.; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

401(k) with company matching

Job summary

The ASIC Product Division in Broadcom is seeking qualified individuals to contribute to SoC and IP development programs. You will join a high‑performance design team delivering state‑of‑the-art subsystems for AI and storage chips.

Responsibilities include building verification environments with SystemVerilog and UVM, designing verification classes, implementing coverage and assertions, and developing random test cases.

Qualifications

• Bachelor's or Master’s degree in EE, CE, or CS with 6+ years of related experience.
• Expertise in Verilog/SystemVerilog and HDL verification techniques.
• Experience with constrained/random verification environments and UVM, OVM, or VMM.
• Strong debugging and performance analysis using HDL simulators.
• Proficient in C++/Java and object-oriented design.

Responsibilities

• Verification environment development using SystemVerilog and UVM.
• Design of verification classes: UVM sequences, agents, scoreboards, and models.
• Implement coverage and assertions in SystemVerilog.
• Develop random and directed test cases to close coverage.
• Analyze and debug simulation failures and coverage results.

Skills

Verilog/SystemVerilog

UVM/OVM/VMM

HDL simulators debugging

OO languages (C++, Java)

Communication skills

Leadership skills

Independent contributor

Education

Bachelor/Master in EE/CE/CS

Job description

The ASIC Product Division in Broadcom is seeking qualified individuals to contribute to SoC and IP development programs. You will join a high‑performance design team delivering state‑of‑the-art subsystems for AI and storage chips.

Responsibilities include building verification environments with SystemVerilog and UVM, designing verification classes, implementing coverage and assertions, and developing random test cases.