Senior ASIC Verification Engineer - UVM & SystemVerilog

Broadcom, Inc.; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grant

Annual equity awards

Medical, dental and vision plans

401(k) with company match

ESPP

Job summary

Broadcom Inc. in Fort Collins seeks an experienced ASIC Verification Engineer to build robust verification infrastructure for a portfolio of ASIC products.

You will design reusable testbenches, implement comprehensive verification plans, and scale coverage to assure first-pass silicon success. You will collaborate with design teams, author directed and constrained-random tests, and develop coverage metrics while advancing SVA-based assertions and regression management.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of ASIC verification experience.
• Or Master’s degree with 6+ years of ASIC verification experience.

Responsibilities

• Design and implement testbenches using SystemVerilog/UVM for scalable ASIC verification.
• Develop verification plans, execute constrained-random tests, and debug complex IP blocks.
• Create coverage plans, write SVA assertions, and drive coverage closure and QA.
• Manage design databases, run regressions, triage failures, and monitor performance.

Skills

SystemVerilog

Verilog

SystemVerilog Assertions (SVA)

Universal Verification Methodology (UV

Education

Bachelor's Degree in Electrical Engineering/Computer Engineering/Computer Science

Master's Degree in related field

Tools

Python scripting

Perl scripting

Tcl scripting

Testbench automation tooling

Job description

Broadcom Inc. in Fort Collins seeks an experienced ASIC Verification Engineer to build robust verification infrastructure for a portfolio of ASIC products.

You will design reusable testbenches, implement comprehensive verification plans, and scale coverage to assure first-pass silicon success. You will collaborate with design teams, author directed and constrained-random tests, and develop coverage metrics while advancing SVA-based assertions and regression management.