Senior IC Verification Engineer (SystemVerilog/UVM)

Broadcom; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Job summary

Broadcom’s ASIC Product Division is seeking qualified individuals to contribute to SoC and IP development programs. The role focuses on state-of-the-art subsystem development for AI and storage chips, enabling high-performance verification environments using SystemVerilog and UVM.

The candidate will design verification classes, implement coverage and assertions, and develop random and directed test cases. Strong HDL and OOP skills, plus leadership and independent work habits, are essential for

Qualifications

• Excellent communication and interpersonal skills.
• Experience communicating in a matrix organization to achieve common goals.
• Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog.
• Experience in designing in constrained random environments using UVM, OVM, or VMM.
• Experience running and debugging using HDL simulators.
• Demonstrated familiarity with OOP languages (C++, Java, etc.) and Proficient with OOP techniques.
• Demonstrated leadership skills.
• Act independently to determine methods and procedures on new or special assignments.
• Must have legal authorization to work in the US. This position does not have funding to support company-sponsored immigration support

Responsibilities

• Verification environment development using modern verification techniques (System Verilog and UVM).
• Designing verification classes such as UVM sequences, agents, scoreboards, and behavioral models.
• Implementing coverage and assertions using System Verilog.
• Developing random & directed test cases to close coverage.
• Analyzing and debugging simulation failures, as well as analyzing coverage results.
• Candidate must be a highly productive individual contributor with demonstrated technical capability in system and sub-block level verification.

Skills

Excellent communication

Matrix organization experience

Critical thinking

Leadership

Independent contributor

Legal to work in US

Education

Bachelor's in EE/CE/CS

Master's in EE/CE/CS

Tools

Verilog/VHDL/SystemVerilog

UVM/OVM/VMM

HDL simulators debugging

C++/Java OOP

OOP techniques

Job description

Broadcom’s ASIC Product Division is seeking qualified individuals to contribute to SoC and IP development programs. The role focuses on state-of-the-art subsystem development for AI and storage chips, enabling high-performance verification environments using SystemVerilog and UVM.

The candidate will design verification classes, implement coverage and assertions, and develop random and directed test cases. Strong HDL and OOP skills, plus leadership and independent work habits, are essential for