Senior IC Packaging Architect - Chiplet & 2.5D Expert (Equity)

Axiado; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Axiado is seeking a Senior IC Packaging Engineer to lead architectural ownership of advanced IC/SiP packaging in a fast-growing startup. You will drive 2D and 2.5D fan-out, chiplet architectures and work with foundries and OSATs to shape product outcomes.

Ideal candidates have 10+ years in packaging, Deep FCBGA/SiP experience, and a strong grasp of design-for-manufacturing and reliability considerations in a high-ambiguity environment.

Qualifications

• BSEE or MSEE in Electrical Engineering.
• 10+ years of IC packaging experience for SoCs/ASICs/memory.
• Deep hands-on expertise in FCBGA and SiP; RDL and chiplet architectures (UCIe).
• Strong understanding of electrical, mechanical, thermal and reliability trade-offs; advanced packaging materials.

Responsibilities

• Serve as technical authority for IC and SiP packaging across products.
• Own package architecture and technology roadmap.
• Lead chiplet-based packaging strategies, including UCIe and silicon interposers.
• Guide hands-on package design and layout for High-speed SerDes/PCIe, LPDDR5/LPDDR5X, UCIe.
• Define substrate stack-ups, materials, bump/RDL architectures; set DFM guidelines.
• Drive SI/PI, thermal, mechanical and reliability trade-offs at system/package levels.
• Lead external engagement with OSATs and foundries for development and ramp.
• Influence product roadmap, risk management and investment decisions.

Skills

IC packaging

SiP packaging

UCIe

2D/2.5D fan-out

Thermal/Mechanical reliability

Education

BSEE/MSEE (PhD a plus)

Tools

Cadence Allegro APD

HFSS

SIwave

Ansys Designer

Job description

Axiado is seeking a Senior IC Packaging Engineer to lead architectural ownership of advanced IC/SiP packaging in a fast-growing startup. You will drive 2D and 2.5D fan-out, chiplet architectures and work with foundries and OSATs to shape product outcomes.

Ideal candidates have 10+ years in packaging, Deep FCBGA/SiP experience, and a strong grasp of design-for-manufacturing and reliability considerations in a high-ambiguity environment.