Package Layout Design Engineer for 2.5D/3D IC Packaging

Amazon; Tempe (AZ); On-site; USD 136,000 - 184,000; Full time

Benefits offered by this job

Health insurance

RSUs

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Annapurna Labs in Tempe, AZ is seeking an experienced IC packaging engineer to execute die floor planning, RDL routing, and tape-out readiness for advanced packaging. You will collaborate with ASIC teams, OSAT partners, and SI/PI to optimize die-to-package interfaces and ensure DFM-compliant designs.

Ideal candidates have 5+ years in IC package layout, hands-on experience with Cadence/SiP tooling, and familiarity with 2.5D/3D-IC, RDL, and interposer technologies.

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• 5+ years in IC package layout and physical design.
• Experience with multi-layer substrates or interposers.

Responsibilities

• Execute package layout tasks across design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
• Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out WLP, and silicon bridge technologies.
• Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
• Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias.
• Support die-level RDL routing and bump planning with ASIC teams to co-optimize die-package interface.
• Cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under senior guidance.
• Maintain package stack-up definitions with SI/PI and materials teams.
• Run DRC, connectivity checks, and support design closure.
• Follow package design rules and work with OSATs to ensure DFM compliance.
• Collaborate with SI/PI to incorporate electrical constraints into layout (impedance, PDN, shielding).

Skills

IC package layout

Physical design

RDL routing

2.5D/3D-IC

DFM constraints

Cross-functional collaboration

Verifications (DRC)

Cadence/SiP tools

Silicon interposer

Impedance control

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Communications Engineering

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Amazon Annapurna Labs in Tempe, AZ is seeking an experienced IC packaging engineer to execute die floor planning, RDL routing, and tape-out readiness for advanced packaging. You will collaborate with ASIC teams, OSAT partners, and SI/PI to optimize die-to-package interfaces and ensure DFM-compliant designs.

Ideal candidates have 5+ years in IC package layout, hands-on experience with Cadence/SiP tooling, and familiarity with 2.5D/3D-IC, RDL, and interposer technologies.