Senior IC Package Design Engineer (RF/SiP)

SpaceX; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

SpaceX in Austin, TX seeks a Sr. IC Package Design Engineer (Silicon Engineering) to lead packaging for in‑house ASICs and RFICs for Starlink and space systems.

You will own package selection, SIP/BGA configurations, layout, and verification, collaborating with cross‑functional teams to optimize signal integrity, power delivery, and manufacturability. You will drive packaging methodology, perform SI/PI analyses, and support tapeout while applying Cadence tools and advanced substrates.

Qualifications

• Bachelor’s degree in electrical, computer engineering or physics.
• 5+ years of IC package design experience.
• Experience with Co-packaged Optics (CPO).
• Strong SI/PI fundamentals.
• Substrate design experience for RF, digital, high-speed and mixed signal die.
• Experience with Cadence APD+/SIP or similar design tools.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS.
• Experience in package design for manufacturing reviews.
• Familiar with BGA package substrate technologies.
• Strong problem solving skills with strong engineering fundamentals.

Responsibilities

• Own and drive advanced package selection, new product BGA configuration and package structure
• Responsible for package/SIP layout, optimization, design verification and tapeout
• Interface and coordinate with cross‑functional groups throughout SpaceX on new product package selection, feasibility analysis and design
• Work cross‑functionally, understand trade‑offs, constraints, and optimizing silicon floor plan, bump and package pin out
• Simulate and optimize signal/power integrity and RF performance of the package design
• Drive methodology, innovations, and productivity improvements in package design

Skills

IC package design

Problem solving

Cross-functional collaboration

Signal integrity

RF design

Education

Bachelor's degree in electrical engineering, computer engineering, or physics

Tools

Cadence APD+/SIP

SIWave

HFSS

ADS

Package design tools

Job description

SpaceX in Austin, TX seeks a Sr. IC Package Design Engineer (Silicon Engineering) to lead packaging for in‑house ASICs and RFICs for Starlink and space systems.

You will own package selection, SIP/BGA configurations, layout, and verification, collaborating with cross‑functional teams to optimize signal integrity, power delivery, and manufacturability. You will drive packaging methodology, perform SI/PI analyses, and support tapeout while applying Cadence tools and advanced substrates.