Senior IC Package Design Engineer – Multi-Die Substrates

Piper Companies; San Jose (CA); On-site; USD 200,000 - 260,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401K

PTO and Holidays

Job summary

Piper Companies is seeking an experienced IC Package Design Engineer to lead the physical layout of advanced multi-die substrates near San Jose, CA. This onsite role focuses on chiplet-based integration and close collaboration with ASIC, signal, and power teams to ensure high-density, high-performance packaging.

The ideal candidate has 8+ years in substrate layout, is proficient in Siemens Xpedition and Cadence Allegro APD, and holds a BSEE or higher. Eligibility for U.S.

Qualifications

• 8+ years of substrate layout experience.
• Eligible to work in the United States with an Active U.S. Government Secret Clearance.
• Strong background in physical layout and collaboration with ASIC, signal, and power teams.
• Proficient in Siemens Xpedition and Cadence Allegro APD.
• Bachelor’s degree in Electrical Engineering preferred.

Responsibilities

• Lead the physical layout of complex multi-die substrates while supporting chiplet-based integration.
• Collaborate with package integration, signal/power integrity, and mechanical teams to ensure successful layout implementation.
• Drive routing feasibility and co-design alignment with floor planning, mechanical, and system constraints.
• Own the full layout process, ensuring performance, manufacturability, and design quality.
• Use industry-standard tools like Siemens Xpedition and Cadence Allegro APD to execute and refine substrate designs.

Skills

Physical layout

Chiplet integration

Collaboration with ASIC/signal/power

Routing/co-design

Education

Bachelor's degree in Electrical Engineering

Tools

Siemens Xpedition

Cadence Allegro APD

Job description

Piper Companies is seeking an experienced IC Package Design Engineer to lead the physical layout of advanced multi-die substrates near San Jose, CA. This onsite role focuses on chiplet-based integration and close collaboration with ASIC, signal, and power teams to ensure high-density, high-performance packaging.

The ideal candidate has 8+ years in substrate layout, is proficient in Siemens Xpedition and Cadence Allegro APD, and holds a BSEE or higher. Eligibility for U.S.