Senior IC Package Design Engineer - Lead AI-Scale Packaging

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Health insurance

Paid time off

Retirement plan

Job summary

Micron Technology, Inc. seeks a Senior Package Design Engineer to lead advanced semiconductor packaging across the full product lifecycle, partnering with silicon teams and OSATs to enable high-volume manufacturing.

You will optimize die floorplans, substrate stacks, and interconnect schemes for DRAM and memory packages used in AI/Data Center, Mobile, and Edge applications. The role demands expertise in floorplanning, high-density routing, and DFMEA, with a track record of delivering designs

Qualifications

• Bachelor’s degree in Electrical/Mechanical/Materials fields with 5+ years of package design experience or Master’s degree with 3+ years.
• Hands-on proficiency with advanced package EDA tools and high-density routing.
• Experience with flip chip, wire bond interconnects, BEOL/RDL flows, and OSAT collaboration.

Responsibilities

• Lead Co-Design from Silicon to System across product lifecycles with silicon teams and customers.
• Optimize floorplans, interconnects, and package architectures from concept to HVM.
• Drive trade-off studies for DRAM products targeting AI/Data Center and edge applications.
• Own package layout, routing, placement, and substrate stack-ups.
• Define wire bond/flip chip schemes and BEOL/RDL flows; produce manufacturing packs.
• Collaborate with SI/PI teams to feed simulation results into design decisions.
• Lead DFMEA reviews and design for manufacturability to ensure HVM readiness.

Skills

Package design

EDA tools

Floorplanning

Collaboration with OSAT

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence Allegro Package Designer+

Cadence Integrity 3D-IC

Siemens/Mentor Xpedition

Job description

Micron Technology, Inc. seeks a Senior Package Design Engineer to lead advanced semiconductor packaging across the full product lifecycle, partnering with silicon teams and OSATs to enable high-volume manufacturing.

You will optimize die floorplans, substrate stacks, and interconnect schemes for DRAM and memory packages used in AI/Data Center, Mobile, and Edge applications. The role demands expertise in floorplanning, high-density routing, and DFMEA, with a track record of delivering designs