Senior IC Layout Engineer — Lead Floorplan & Tapeout (Remote)

Impinjexternal; United States; On-site; USD 158,700 - 238,100; Full time

Job summary

Impinj is a leading RFID and IoT innovator seeking an senior Layout Design Engineer. You will own complex IC floorplanning and lead tape-out efforts across RF, analog, and mixed-signal blocks, working with circuit teams to ensure reliability and performance.

Expect close collaboration with CAD, verification, and manufacturing teams in a fast-paced environment. You will mentor other layout engineers and drive full-chip integration strategies while navigating advanced nodes and tape-out readiness.

Qualifications

• Degree in computer or electrical engineering with 12+ years of relevant experience.
• Experience in custom analog, RF, and mixed-signal layout and leading ICs to tapeout.
• Proficient with tapeout flows and final database preparation.
• Ability to mentor other layout engineers and lead IC integration.

Responsibilities

• Leverage Top-Down Bottom-Up floorplan methods to create and refine RFID/Reader IC floorplans.
• Collaborate with analog and digital teams on floor planning, power distribution, and signal routing.
• Coordinate with cross-functional teams to track layout activities and schedule tape-out.
• Conduct layout reviews for EM, matching, and signal integrity; perform DRC/LVS checks.
• Perform transistor-level layout of RF, mixed-signal, and analog blocks for high-performance
• Contribute to roadmap of IC layout methodology with technology and CAD teams.

Skills

Custom analog, RF, mixed-signal layout

Lead complex ICs from conception to

Tapeout flows

Mentor layout engineers

Full-chip/SOC floorplanning and interg

Education

Bachelor’s or Master’s degree in computer or electrical engineering

Tools

Cadence Virtuoso

PVS

Siemens Calibre DRC/LVS

Job description

Impinj is a leading RFID and IoT innovator seeking an senior Layout Design Engineer. You will own complex IC floorplanning and lead tape-out efforts across RF, analog, and mixed-signal blocks, working with circuit teams to ensure reliability and performance.

Expect close collaboration with CAD, verification, and manufacturing teams in a fast-paced environment. You will mentor other layout engineers and drive full-chip integration strategies while navigating advanced nodes and tape-out readiness.