Senior IC Design Engineer, R&D – P&R, IR/EM, Equity

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Job summary

Broadcom is seeking a senior physical design engineer in the Irvine/San Jose area to drive the implementation of complex chips from netlist to GDSII. You will lead floorplanning, partitioning, and block pin assignments, and perform PnR, timing closure, and verification with strong scripting to automate flows.

Experience in low-power IC design and Mentor Calibre for physical verification is highly valued. A bachelor’s degree with 8+ years (or a master’s with 6+ years) is required, with location

Qualifications

• Bachelor’s degree and 8+ years of related experience, or Master’s with 6+ years of experience.
• Experience with chip flow from netlist to GDSII and understanding of design flow in all stages.
• Familiar with scripting to automate physical design flow and increase efficiency.
• Expertise in low-power IC design is desirable.

Responsibilities

• Work as part of a physical design team implementing chips from netlist to GDSII with understanding of technology elements and design flow.
• Responsible for floorplanning, design partitioning, and block pin assignment.
• Perform block PnR, timing closure, and physical verification.
• Perform block IR/EM analysis and consider chip-level IR/EM as a plus.
• Write scripts to automate the physical design flow using TCL, Perl, or Python.

Skills

Floorplanning

Partitioning

PnR (Place & Route)

Timing closure

Physical verification

IR/EM analysis

Scripting Tcl/Perl/Python

Low-power IC design

Education

Bachelor's degree

Master's degree

Tools

Mentor Calibre

Job description

Broadcom is seeking a senior physical design engineer in the Irvine/San Jose area to drive the implementation of complex chips from netlist to GDSII. You will lead floorplanning, partitioning, and block pin assignments, and perform PnR, timing closure, and verification with strong scripting to automate flows.

Experience in low-power IC design and Mentor Calibre for physical verification is highly valued. A bachelor’s degree with 8+ years (or a master’s with 6+ years) is required, with location