P&R Design Engineer: Place & Route, Timing Closure

Broadcom Inc.; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental & vision plans

401(k) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays, sick leave & vacation

Job summary

Broadcom Inc. is seeking an experienced Design Implementation engineer in the San Jose area to drive place-and-route and timing closure at block and SoC levels.

You will handle floorplanning, partitioning, placement, clock tree synthesis, routing, and timing analysis to ensure Right-first-time silicon. The role requires strong expertise with Primetime, ICC2, Innovus, and related tools, plus experience with 7nm or lower process technologies.

Qualifications

• Extremely proficient in design implementation activities at block and SoC level.
• Experience with floor-planning, partitioning, placement, clock tree synthesis, route, physical verification, and constraints validation.
• Hands-on with timing analysis and ECO implementation.

Responsibilities

• Work on Design Implementation activities related to place and route and timing closure.
• Drive tools/methodologies to achieve PPA metrics; perform equivalence checks, STA, timing closure, and power optimization.
• Implement timing and functional ECOs and contribute to tapeout readiness.

Skills

Place & route

Timing closure

Floorplanning

Partitioning

Placement

Clock tree synthesis

Timing analysis

Power optimization

Eco implementation

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Primetime

ICC2

Innovus

Caliber

LEC

PrimeTime

Job description

Broadcom Inc. is seeking an experienced Design Implementation engineer in the San Jose area to drive place-and-route and timing closure at block and SoC levels.

You will handle floorplanning, partitioning, placement, clock tree synthesis, routing, and timing analysis to ensure Right-first-time silicon. The role requires strong expertise with Primetime, ICC2, Innovus, and related tools, plus experience with 7nm or lower process technologies.