Senior VLSI Design Engineer — IO & Datapath

Western Digital; Honolulu (HI); On-site; USD 120,000 - 180,000; Full time

Job summary

Western Digital is seeking an experienced engineer to drive IO and datapath solutions for memory in advanced CMOS nodes. You will collaborate with teams to meet specifications, participate in design reviews, and proactively resolve design issues while proposing innovative design methodologies.

The role requires hands‑on experience with DDR/HSIO/TM/ONFI, GPIOs, ZQ/Vref, and SI/PI analysis; familiarity with Cadence Virtuoso, Synopsys HSPICE/Spectre, and mixed‑mode sim is a plus.

Qualifications

• Bachelor's or Master's in Electronics & Telecommunication or Electrical engineering with 10+ years of experience.
• Hands-on knowledge of IO and datapath design and protocols like DDR, HSIO, TM, ONFI.
• Experience with GPIOs, HSIOs, ZQ and Vref blocks.
• Awareness of channel impairments and equalization schemes (FFE, CTLE, DFE).
• Experience in SI/PI analysis with IBIS/SPF models.
• Proficiency with Cadence Virtuoso and Synopsys/HSPICE/Spectre tools; statistical simulation.
• Mixed‑mode simulation and analog/digital co‑simulation a plus.
• Creating EDA models (Verilog, Liberty) a plus.
• Strong theoretical background with practical, pragmatic approach.
• Good written/verbal communication and multi-geography collaboration.

Responsibilities

• Drive IO and datapath solutions for next‑generation memory in advanced CMOS nodes.
• Collaborate with team to meet IO/DP specifications and product requirements.
• Participate in technical discussions and design reviews; proactively resolve design issues.
• Contribute innovative design solutions and methodologies to improve reliability and performance.
• Coordinate cross‑geography communication and maintain high standards of documentation.

Skills

IO design

Datapath design

High‑speed IO

Communication

Education

Bachelor's/Master's in Electronics & Telecommunication/Electrical

Tools

Cadence Virtuoso

Synopsys HSPICE

Spectre

Verilog/Liberty

Job description

Western Digital is seeking an experienced engineer to drive IO and datapath solutions for memory in advanced CMOS nodes. You will collaborate with teams to meet specifications, participate in design reviews, and proactively resolve design issues while proposing innovative design methodologies.

The role requires hands‑on experience with DDR/HSIO/TM/ONFI, GPIOs, ZQ/Vref, and SI/PI analysis; familiarity with Cadence Virtuoso, Synopsys HSPICE/Spectre, and mixed‑mode sim is a plus.