Memory Control Design Engineer

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Competitive annual discretionary bonus

Annual RSU grants

Highly competitive benefits package

Job summary

Qualcomm is seeking an ASIC Design Engineer to join the QCT Memory Controller Design Team in San Diego, California. The engineer will work on architecture, design, and deployment of the next generation high-speed DDR Controllers.

Candidates should have experience with DDR controller architectures and CPU interfaces. A Bachelor’s degree in Science or Engineering with relevant experience is required, and competitive pay between $115,600 and $173,400 is offered along with a strong benefits package.

Qualifications

• 3-8 years of experience in ASIC design or related disciplines.
• 2+ years of ASIC design, verification, validation, integration, or related work experience for Bachelor's degree holders.
• 1+ year of ASIC design, verification, validation, integration, or related work experience for Master's degree holders.

Responsibilities

• Develop architecture, design, and deployment of Memory Controllers.
• Deliver RTL and collaborate with verification engineers.
• Provide support in integration, timing closure, and physical design.

Skills

DDR controller architectures

x86 or ARM CPU/bus architectures

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

Ph.D. in Science, Engineering, or related field

Job description

Company

Qualcomm Technologies, Inc.

Job Overview

QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high‑speed DDR Controllers. The front‑end of the DDR controller interfaces to the rest of the system such as CPU, DSP, multimedia processors and the engineer is expected to enable high‑speed (1GHz+) designs in QCT products.

The candidate will work on the architecture, design, and deployment of Memory Controllers for LPDDR/PCDDR technologies into QCT products. Responsibilities include developing design specifications, driving micro‑architecture of portions of the logic design, implementing and delivering RTL, collaborating with verification engineers to deliver high‑quality designs, debugging designs, providing debug support in integration, synthesis, timing closure, physical design support, gate‑level simulations, power analysis, and participating in C/C++ modeling of memory controller IP. Regular contributions to overall improvement in design methodology to drive productivity and quality of results are expected.

Required Experience

• Experience with DDR controller architectures, especially the front‑end interfacing to the CPU, DSP, and multimedia processors.
• Experience with x86 or ARM CPU/bus architectures.
• 3–8 years of experience in ASIC design or related disciplines.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• Ph.D. in Science, Engineering, or related field.

Salary & Benefits

Pay range: $115,600.00 – $173,400.00

In addition to base salary, a competitive annual discretionary bonus program and opportunity for annual RSU grants are offered. A highly competitive benefits package supports success at work, at home, and on the go.

EEO Statement

Qualcomm is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.