Senior First-Silicon Design Verification Engineer

Apple, Inc.; Cary (NC); On-site; USD 120,000 - 190,000; Full time

Job summary

Apple in Cary, NC is seeking a design verification engineer to drive DV for IP and SoC projects from pre-silicon to tape-out. You will define DV methodology, build verification environments, and execute test plans with robust coverage goals.

You will use SystemVerilog/UVM, build scalable test-benches, debug regressions, and report progress with metrics. Experience with LLMs for efficiency is a plus; collaboration across teams is essential.

Qualifications

• BS degree in technical subject and a minimum 10 years relevant industry experience or equivalent.
• Deep knowledge of SystemVerilog, OOP and UVM.
• Experience developing scalable and portable test-benches.
• Experience with verification tools such as simulators, waveform viewers, coverage collection, gate-level simulations.
• Experience using LLMs for efficiency and quality.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Job description

Apple in Cary, NC is seeking a design verification engineer to drive DV for IP and SoC projects from pre-silicon to tape-out. You will define DV methodology, build verification environments, and execute test plans with robust coverage goals.

You will use SystemVerilog/UVM, build scalable test-benches, debug regressions, and report progress with metrics. Experience with LLMs for efficiency is a plus; collaboration across teams is essential.