Senior Verification Platform Architect for Silicon DV

Apple Inc.; Cupertino (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Apple Inc. is seeking a Verification Platform Engineer to advance DV methodologies and tooling for Apple silicon. You will improve testbench design and infrastructure to enable faster simulation throughput, collaborating with silicon engineers and internal teams across sites.

The role requires a Bachelor's in computer/electrical engineering and strong experience with SystemVerilog, EDA tooling, C++, and Python scripting, with occasional travel to US sites and based in Cupertino, CA.

Qualifications

• Bachelor's degree in computer/electrical engineering.
• Experience with SystemVerilog and EDA tooling.
• Experience with C++ and Python scripting.

Responsibilities

• Advance DV methodologies and tooling for Apple silicon.
• Enable faster simulation throughput via testbench design, infrastructure improvements, and platform R&D.
• Work with silicon engineering and internal teams.

Skills

SystemVerilog

C++

Python

Education

Bachelor's degree in computer/electrical engineering

Tools

EDA tooling

Job description

Apple Inc. is seeking a Verification Platform Engineer to advance DV methodologies and tooling for Apple silicon. You will improve testbench design and infrastructure to enable faster simulation throughput, collaborating with silicon engineers and internal teams across sites.

The role requires a Bachelor's in computer/electrical engineering and strong experience with SystemVerilog, EDA tooling, C++, and Python scripting, with occasional travel to US sites and based in Cupertino, CA.