Senior GPU RTL Design Engineer - Pixel Pipeline

Bzpp; United States; On-site; USD 139,000 - 208,000; Full time

Job summary

Samsung Austin Research and Development Center (SARC/ACL) seeks a Senior Engineer, GPU RTL Design, to contribute RTL blocks and subsystems for next-generation mobile GPU IPs. You will translate architectural concepts into efficient hardware, collaborating with cross-functional hardware and software teams to deliver production-ready designs.

You will own microarchitecture definition, RTL development, integration, debug, and validation across multiple IP generations, focusing on pixel processing,

Qualifications

• 2+ years of hands-on RTL design experience for complex SoC/GPU architectures.
• Proficient in Verilog/SystemVerilog and RTL development.
• Experience with front-end ASIC design flows: linting, synthesis, timing analysis.
• Knowledge of GPU pipelines, memory, and pixel processing.
• Strong communication and collaboration in a global team.

Responsibilities

• Design and development of RTL blocks and subsystems for GPU IPs.
• Collaborate with hardware and software teams across domains.
• Define microarchitecture and RTL implementation including pixel pipeline.
• Support verification and validation and resolve functional issues.
• Address timing, power, performance, and area tradeoffs with teams.

Skills

RTL Design

Verilog/SystemVerilog

GPU architecture

Microarchitecture

Synthesis & timing

Team collaboration

Analytical skills

Documentation

Education

Bachelor's or Master's in CS/CE

Tools

Verilog

SystemVerilog

Synthesis tools

Timing analysis

Job description

Samsung Austin Research and Development Center (SARC/ACL) seeks a Senior Engineer, GPU RTL Design, to contribute RTL blocks and subsystems for next-generation mobile GPU IPs. You will translate architectural concepts into efficient hardware, collaborating with cross-functional hardware and software teams to deliver production-ready designs.

You will own microarchitecture definition, RTL development, integration, debug, and validation across multiple IP generations, focusing on pixel processing,