Senior Design Verification Engineer - Full-Chip & FPGA

Redolent Infotech Pvt. Ltd.; Folsom (CA); Sur place; USD 110 000 - 170 000; Plein temps

Résumé du poste

Redolent Infotech Pvt. Ltd. in Folsom, CA seeks a Design Verification Engineer to drive full-chip verification using industry-standard methodologies.

You will develop UVM/OVM/VMM test benches, verify interfaces such as PCIe, NoC/AXI, DDR4, and work with tools like Synopsys VCS, Cadence IES, and formal checkers.

Candidates should have strong knowledge of verification techniques, SystemC-based modeling, and FPGA programming experience.

Qualifications

• Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench
• Strong understanding of verification techniques including assertion and metric-driven verification
• Verification experience with AXI, NoC, HBM, DDR4, PCIe is a plus
• Experience with formal property checking tools such as Cadence IEV, Jasper, and Synopsys Magellan is a plus
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
• Some DFX/DFT and UPF/power-aware-simulation experience is a plus

Connaissances

UVM/OVM/VMM

SystemVerilog

ASIC verification

SystemC modeling

FPGA programming

Formation

Bachelor's in EE/CS

Outils

Synopsys VCS

Cadence IES

Jasper

Magellan

Description du poste

Redolent Infotech Pvt. Ltd. in Folsom, CA seeks a Design Verification Engineer to drive full-chip verification using industry-standard methodologies.

You will develop UVM/OVM/VMM test benches, verify interfaces such as PCIe, NoC/AXI, DDR4, and work with tools like Synopsys VCS, Cadence IES, and formal checkers.

Candidates should have strong knowledge of verification techniques, SystemC-based modeling, and FPGA programming experience.