Senior Digital Verification Engineer — UVM & Full-Chip

Snowcap Compute; San Francisco, Northern (CA, KY); Hybrid; USD 130,000 - 200,000; Full time

Benefits offered by this job

Medical, dental, and vision

401(k)

Relocation assistance

Job summary

Snowcap Compute in the San Francisco Bay Area is seeking a Digital Verification Engineer to own UVM testbenches for RTL blocks and the full-chip netlist. You will define functional coverage, write directed and constrained-random tests, and manage the regression infrastructure that runs nightly, collaborating with the Digital Architect and RTL/design teams.

Expect hands-on waveform debugging, root-cause analysis, and a drive to close coverage holes.

Qualifications

• Strong UVM and SystemVerilog verification methodology experience on production silicon that taped out and ran.
• Track record of coverage-driven verification—defining the coverage model, closing it, and defending the closure.

Responsibilities

• Own UVM testbench development for RTL blocks and the full-chip netlist — drivers, monitors, scoreboards, and reference models.
• Define functional coverage goals against the microarchitecture spec, track them, and close holes.
• Write directed and constrained-random tests that exercise SFQ-specific logic behaviors and corner cases.
• Build and own the chip-level simulation environment and the regression infrastructure that runs nightly.
• Drive debug cycles with RTL engineers: find root cause and produce verifiable artifacts.
• File, track, and triage functional bugs through to closure — push back when an RTL fix is a spec problem.
• Apply formal verification where it earns its keep — properties, equivalence, model checking.
• Set the verification methodology and infrastructure standards at Snowcap.

Skills

UVM testbench development

SystemVerilog

Coverage-driven verification

Constrained-random testing

Regression automation

Python/Perl scripting

Tools

Formal verification tools

Job description

Snowcap Compute in the San Francisco Bay Area is seeking a Digital Verification Engineer to own UVM testbenches for RTL blocks and the full-chip netlist. You will define functional coverage, write directed and constrained-random tests, and manage the regression infrastructure that runs nightly, collaborating with the Digital Architect and RTL/design teams.

Expect hands-on waveform debugging, root-cause analysis, and a drive to close coverage holes.