Senior ASIC Verification Engineer (UVM, SystemVerilog)

WarmStart Ltd; Milpitas (CA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Sandisk in Milpitas, CA is seeking a Senior IP Verification Engineer to strengthen the design verification team, focusing on functional correctness and performance of complex digital IP blocks.

You will develop verification plans and UVM-based testbenches, create UVCs, implement constrained-random stimulus, debug RTL issues, and drive coverage and regression, while mentoring junior engineers.

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.
• 10+ years of IP verification experience.

Responsibilities

• Develop verification plans and testbenches using UVM.
• Create reusable verification components (UVCs) including agents, monitors, drivers, and scoreboards.
• Design constrained-random stimulus and coverage-driven verification strategies.
• Debug RTL issues and perform root cause analysis with design teams.
• Develop and maintain regression test suites and coverage metrics.
• Mentor junior engineers on UVM best practices.
• Review and improve verification infrastructure and coding standards.
• Contribute to IP-level and SoC-level verification.

Skills

SystemVerilog

UVM

Verification IP

Simulation tools

PCIe

DDR

AXI/AMBA

Python scripting

Debugging

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Cadence

Synopsys

Mentor

Job description

Sandisk in Milpitas, CA is seeking a Senior IP Verification Engineer to strengthen the design verification team, focusing on functional correctness and performance of complex digital IP blocks.

You will develop verification plans and UVM-based testbenches, create UVCs, implement constrained-random stimulus, debug RTL issues, and drive coverage and regression, while mentoring junior engineers.