Senior Verification Architect - NoC & DDR5/HBM4

Advanced Micro Devices; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices in San Jose, CA is seeking a Senior Staff Silicon Design Verification Engineer to lead verification of high-speed memory controllers and related IP at IP and SoC levels. You’ll architect and implement verification environments using UVM, formal methods, and assertion-based techniques, and drive first-pass silicon success.

You will mentor teams, coordinate with design, architecture, and software groups, and shape verification strategy with state-of-the-art tools such as

Qualifications

• The ideal candidate has a proven track record in driving verification strategies for pre-silicon IP or SoC designs.
• Experience leading verification teams with 5+ engineers.
• Strong knowledge of memory controller protocols and calibration (DDR/LPDDR/HBM).
• Experience developing UVM and SystemVerilog testbenches and using simulation tools like Synopsys VCS or Cadence Xcelium.
• Familiarity with verification management tools and regression databases.
• Experience with formal property checking tools (VC Formal, JasperGold, Questa Formal) is a plus.

Responsibilities

• Lead verification of high-speed Crypto, NoC, and memory controller designs (DDR5/LPDDR6/HBM4).
• Architect and develop IP- and SoC-level verification environments.
• Lead and manage verification teams: planning, execution, tracking, closure, delivery.
• Create and execute comprehensive verification plans with testbenches and tests.
• Collaborate with design, architecture, and software teams to define verification strategies.
• Apply UVM, formal verification, and assertion-based methods.
• Mentor junior engineers and foster a collaborative team environment.

Skills

Verification leadership

UVM & SystemVerilog

Formal verification

Memory controllers DDR/LPDDR/HBM

Team mentoring

VCS / Xcelium

Education

BS in Electrical/Computer Engineering or CS

Tools

Synopsys VCS

Cadence Xcelium

VC Formal

JasperGold

Questa Formal

Job description

Advanced Micro Devices in San Jose, CA is seeking a Senior Staff Silicon Design Verification Engineer to lead verification of high-speed memory controllers and related IP at IP and SoC levels. You’ll architect and implement verification environments using UVM, formal methods, and assertion-based techniques, and drive first-pass silicon success.

You will mentor teams, coordinate with design, architecture, and software groups, and shape verification strategy with state-of-the-art tools such as