AI-Driven Front-End RTL Infrastructure CAD Engineer

Apple Inc.; Cupertino (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

Apple Inc. in Cupertino is seeking a Front-End RTL Infrastructure - CAD Engineer to help design and support RTL design environments, ensuring scalable toolchains and reliable infrastructure for design and verification teams.

You will drive Perforce administration, configuration management, and AI-enabled improvements across RTL flows, collaborating with designer and DV groups to implement robust, scalable solutions.

Qualifications

• BS degree plus 3 years of relevant experience.
• Expertise in Python or Perl programming.
• Knowledge of Verilog and SystemVerilog.

Responsibilities

• Develop and support infrastructure used by RTL design and DV teams.
• Manage RTL gatekeeping infrastructure and soft IP release methods.
• Contribute to Perforce administration and configuration management.
• Promote AI-driven improvements to engineering productivity and infrastructure reliability.
• Create and maintain training materials and coordinate vendor trainings.

Skills

Python

Perl

Verilog

SystemVerilog

Education

BS degree

MSEE/CE/CS preferred

Tools

Perforce

Job description

Apple Inc. in Cupertino is seeking a Front-End RTL Infrastructure - CAD Engineer to help design and support RTL design environments, ensuring scalable toolchains and reliable infrastructure for design and verification teams.

You will drive Perforce administration, configuration management, and AI-enabled improvements across RTL flows, collaborating with designer and DV groups to implement robust, scalable solutions.