Senior CAD Frontend Engineer RTL to Handoff with AI Tools

Socket.dev

Santa Clara (CA)

On-site

USD 180,000 - 260,000

Full time

12 days ago
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Job summary

Velaura is building custom silicon for Physical and Embodied AI, delivering RTL-to-hand-off automation that accelerates the design cycle. You will own front end automation spanning RTL entry through DFT handoff, including design and verification flows and AI-assisted tooling.

Success is measured by increased productivity and stable toolchains across the design cycle, collaborating closely with DFT and physical design teams to ensure smooth handoffs.

Qualifications

  • 8+ years in design verification, design or CAD engineering

Responsibilities

  • Own the RTL design flows including build, lint, CDC and formal checks.
  • Own register generation and the generator driven flows behind interfaces and integration.
  • Own the DV flows including testbench build, regression execution and coverage collection.
  • Own emulation and FPGA prototyping build and bring up.
  • Build and deploy AI assisted tooling across design and verification workflows, working with CAD and Engineering Infrastructure on compute and model access.
  • Keep these flows available through the design cycle, managing tool versions and turning around bug, upgrade and maintenance requests quickly.
  • Measure and improve design and verification productivity, and move proven workflows into standard practice.
  • Partner with DFT and physical design on handoff readiness, owning the DFT side flows that sit in the front end.

Skills

SystemVerilog
RTL design
Python
EDA tools
Linux
UVM
Cocotb
Python-based verification

Tools

LSF/Slurm
Grafana

Job description

Velaura is building custom silicon for Physical and Embodied AI, delivering RTL-to-hand-off automation that accelerates the design cycle. You will own front end automation spanning RTL entry through DFT handoff, including design and verification flows and AI-assisted tooling.

Success is measured by increased productivity and stable toolchains across the design cycle, collaborating closely with DFT and physical design teams to ensure smooth handoffs.

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