Senior Front-End Verification & Design Automation Engineer

Altera Corporation; San Jose (CA); On-site; USD 188,000 - 271,000; Full time

Job summary

Altera Corporation in San Jose, CA seeks a Senior Design Automation Engineer to advance front-end RTL design verification and automation across FPGA flows. You will build scalable scripts and automation frameworks, collaborating with design and verification teams to raise productivity and reduce cycle times.

The role emphasizes applying AI/ML-driven features within EDA tools, integrating new capabilities, and partnering with vendors to optimize toolchains for next‑gen FPGA products.

Qualifications

• 8+ years of hands-on experience with Front End RTL and/or Design Verification EDA tools.
• Experience utilizing AI/ML features within commercial EDA tools and/or data pipelines for design automation.
• Proficiency with Unix/Linux and scripting languages (Python, Tcl, Shell).
• Experience building flow automation tools and integrating into complex design pipelines.

Responsibilities

• Develop, deploy, and support advanced design automation flows for digital semiconductor design.
• Create scripts and automation frameworks to streamline design processes.
• Evaluate and enhance EDA tools to improve productivity and quality.
• Automate repetitive tasks with robust, scalable solutions.
• Collaborate with design and verification teams to remove workflow bottlenecks.
• Drive continuous improvements in automation infrastructure and practices.

Skills

Python

Unix/Linux

Shell scripting

AI/ML in EDA

Flow automation

Education

Bachelor's or Master's in CS/EE

Tools

VCS

Xcelium

SpyGlass

Job description

Altera Corporation in San Jose, CA seeks a Senior Design Automation Engineer to advance front-end RTL design verification and automation across FPGA flows. You will build scalable scripts and automation frameworks, collaborating with design and verification teams to raise productivity and reduce cycle times.

The role emphasizes applying AI/ML-driven features within EDA tools, integrating new capabilities, and partnering with vendors to optimize toolchains for next‑gen FPGA products.