Senior ASIC Signoff Architect – High-Speed IP & SoCs

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys Inc. is seeking an experienced ASIC Digital Signoff Engineer to contribute to next-generation SerDes, memory interface controllers, PHYs, and subsystems.

You will define best-in-class design standards, collaborate with global teams, and drive high-speed digital IP design signoff across foundries. With 12+ years in CAD flows and STA/EM/IR expertise, you will develop scalable methodologies, produce clear documentation, and train teams.

Qualifications

• BS or MS in Electrical Engineering with 12+ years of hands-on CAD experience.
• Experience enabling advanced node STA/Timing signoff at the SoC level.
• Familiarity with IP deliverables, ASIC implementation, physical design flows, memories and libraries.
• Knowledge of EMIR & Thermal sign-off flows is a plus.

Responsibilities

• Develop and deploy signoff methodologies for advanced IP designs across foundries.
• Drive best-in-class PPA for IP designs with leading-edge teams.
• Evaluate signoff timing, power, physical verification, EM/IR, and ECOs.
• Create and maintain digital design methodologies, docs, scripts, and training.
• Act as liaison between Synopsys tools and IP design teams.
• Continuously improve design processes for efficiency and performance.

Skills

STA/Timing signoff

CAD flows for high-speed IP/SOC

Cross-functional collaboration

Documentation & training

Education

BS or MS in EE

Tools

Synopsys tools

StarRC

ICV

EMIR

Job description

Synopsys Inc. is seeking an experienced ASIC Digital Signoff Engineer to contribute to next-generation SerDes, memory interface controllers, PHYs, and subsystems.

You will define best-in-class design standards, collaborate with global teams, and drive high-speed digital IP design signoff across foundries. With 12+ years in CAD flows and STA/EM/IR expertise, you will develop scalable methodologies, produce clear documentation, and train teams.