Frontend ASIC Implementation & Static Verification Engineer

Meta; Sunnyvale (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

Meta in Sunnyvale, CA seeks an ASIC Frontend Implementation Engineer specializing in RTL to netlist flow for data center SoCs. You will collaborate with design, DV, and emulation teams to deliver optimized gate-level netlists capable of meeting timing, area and power targets.

Responsibilities include RTL lint, CDC/RDC analysis, DFT coverage improvements, and automation scripting to streamline frontend tooling.

Qualifications

• BS in computer science, computer engineering or a related field, or equivalent practical experience.
• Experience with front-end implementation from RTL to netlist, including timing and optimization.

Responsibilities

• Perform flat and hierarchical CDC and reset domain crossing analyses and sign-off.
• Conduct RTL linting, DFT analysis, and improve coverage for stuck-at faults.
• Run logic/physical synthesis and generate optimized gate-level netlists.
• Develop automation scripts and methodologies for FE-tools.

Skills

RTL to netlist

RTL Lint

CDC analysis

Timing constraints

Synthesis

DFT analysis

Automation scripts

Education

Bachelor's degree in CS/CE or related

Tools

Lint

CDC tools

RDC

DFT tools

Synthesis tools

Job description

Meta in Sunnyvale, CA seeks an ASIC Frontend Implementation Engineer specializing in RTL to netlist flow for data center SoCs. You will collaborate with design, DV, and emulation teams to deliver optimized gate-level netlists capable of meeting timing, area and power targets.

Responsibilities include RTL lint, CDC/RDC analysis, DFT coverage improvements, and automation scripting to streamline frontend tooling.