Senior FPGA Verification Engineer — RTL/UVM Lead

Anduril Industries; Boulder (CO); On-site; USD 165,000 - 218,000; Full time

Benefits offered by this job

Equity grants

Comprehensive benefits

Job summary

Anduril Industries is seeking a Senior FPGA Verification Engineer to help design new product lines. You will work with an interdisciplinary team to define, complete the design and analysis, build prototypes for ground and flight testing, and mature them into commercial products.

The role requires 8+ years of HDL experience, RTL verification with VHDL/Verilog, and a track record of leading verification efforts in FPGA/ASIC environments. U.S. Secret clearance eligibility is required.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 8+ years of experience developing HDL firmware for FPGA devices
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
• Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
• Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity
• Eligible to obtain and maintain an active U.S. Secret security clearance

Responsibilities

• Verification environment architecture and design using SystemVerilog or OVM/UVM
• Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
• Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
• Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Skills

SystemVerilog

VHDL

RTL verification

Testbench design

Verilog

Git/SVN

Security clearance

Education

Bachelor's in Electrical/Computer Engineering

Tools

QuestaSim

Synplify

Quartus

Vivado

Job description

Anduril Industries is seeking a Senior FPGA Verification Engineer to help design new product lines. You will work with an interdisciplinary team to define, complete the design and analysis, build prototypes for ground and flight testing, and mature them into commercial products.

The role requires 8+ years of HDL experience, RTL verification with VHDL/Verilog, and a track record of leading verification efforts in FPGA/ASIC environments. U.S. Secret clearance eligibility is required.