Senior FPGA Verification Engineer | RTL & SystemVerilog

Slope; Waltham (MA); On-site; USD 166,000 - 220,000; Full time

Benefits offered by this job

Equity grants

Benefits package

Job summary

Anduril's Imaging team is seeking an FPGA Verification Engineer to help define and mature new product lines from prototype to flight-ready hardware. You will contribute to architectural verification, write test plans, and build verifiable RTL blocks in VHDL/SystemVerilog across a cross-disciplinary team.

You will lead verification strategy, develop testbenches, and collaborate with hardware and software engineers to deliver reliable RTL implementations while advancing design methodologies and

Qualifications

• A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
• 8+ years of experience developing HDL firmware for FPGA devices.
• Experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
• Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
• Eligible to obtain and maintain an active U.S. Secret security clearance

Responsibilities

• Verification environment architecture and design using SystemVerilog or OVM/UVM
• Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
• Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
• Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Skills

FPGA verification

SystemVerilog

VHDL

RTL testbenches

Constrained-random testing

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

QuestaSim

Synplify

Quartus

Vivado

Job description

Anduril's Imaging team is seeking an FPGA Verification Engineer to help define and mature new product lines from prototype to flight-ready hardware. You will contribute to architectural verification, write test plans, and build verifiable RTL blocks in VHDL/SystemVerilog across a cross-disciplinary team.

You will lead verification strategy, develop testbenches, and collaborate with hardware and software engineers to deliver reliable RTL implementations while advancing design methodologies and