Senior FPGA Verification Engineer - RTL Testbenches

Mosaic.tech; Boulder (CO); On-site; USD 165,000 - 218,000; Full time

Job summary

Anduril Industries is hiring a Senior FPGA Verification Engineer to design and verify next‑gen product lines. You will work with an interdisciplinary team to define, complete the design and analysis, build prototypes for ground and flight testing, and mature these prototypes into final products.

The role emphasizes verification of RTL blocks using VHDL/SystemVerilog, developing testbenches, and contributing to project estimates while providing technical leadership for verification teams.

Qualifications

• A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
• 8+ years of experience developing HDL firmware for FPGA devices.
• Experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA/ASIC environment.
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Experience using Git or Subversion for source control and collaboration.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Responsibilities

• Verify RTL blocks using VHDL/SystemVerilog and build verification environments.
• Develop testbenches and write test plans, code coverage, and functional coverage.
• Collaborate with hardware/software teams to mature prototypes into producible designs.
• Lead verification activities and plan project work with status reporting.

Skills

HDL firmware

RTL verification

VHDL

SystemVerilog

Testbench

Git/SVN

Security clearance

Lab practices

Education

Bachelor's in Electrical/Computer Engineering

Tools

QuestaSim

Synplify

Vivado

Quartus

Job description

Anduril Industries is hiring a Senior FPGA Verification Engineer to design and verify next‑gen product lines. You will work with an interdisciplinary team to define, complete the design and analysis, build prototypes for ground and flight testing, and mature these prototypes into final products.

The role emphasizes verification of RTL blocks using VHDL/SystemVerilog, developing testbenches, and contributing to project estimates while providing technical leadership for verification teams.