Senior FPGA Verification Engineer - Equity & Benefits

Mosaic.tech; Waltham (MA); On-site; USD 191,000 - 253,000; Full time

Benefits offered by this job

Equity grants

Competitive benefits

Job summary

Anduril Industries is seeking a Senior FPGA Verification Engineer to help design new product lines. You will work with a cross-disciplinary team to define, verify, and mature prototypes through ground and flight testing, delivering robust RTL verification for FPGA/ASIC blocks.

The role requires 8+ years of HDL firmware experience, expertise in VHDL/Verilog, and a track record building testbenches and coverage. Candidates should be eligible for a U.S.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field.
• 8+ years of HDL firmware development for FPGA/ASIC.
• Experience developing and simulating RTL using VHDL/Verilog.
• Proven ability to design verification testbenches for RTL blocks.
• Experience with chip-level verification methodologies (CR testing, coverage, assertions).
• Experience using Git or Subversion to manage source code.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Responsibilities

• Define, build, and analyze verification environments for RTL blocks.
• Develop testbenches, write tests, and track coverage and assertions.
• Collaborate with interdisciplinary teams to mature prototypes into products.
• Provide technical leadership for project verification teams.
• Contribute to engineering estimates for new programs.

Skills

HDL firmware development

RTL verification

SystemVerilog

VHDL

Testbench design

Git

Security clearance eligible

Education

Bachelor's in Electrical Engineering or Computer Engineering

Tools

QuestaSim

Synplify

Quartus

Vivado

Job description

Anduril Industries is seeking a Senior FPGA Verification Engineer to help design new product lines. You will work with a cross-disciplinary team to define, verify, and mature prototypes through ground and flight testing, delivering robust RTL verification for FPGA/ASIC blocks.

The role requires 8+ years of HDL firmware experience, expertise in VHDL/Verilog, and a track record building testbenches and coverage. Candidates should be eligible for a U.S.